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MPMC R20 Regulation Question Papers (Regular)

SPECIAL ADDRESSING MODES IN P-DSPs

In addition to the addressing modes such as direct, indirect and immediate supported by the conventional microprocessors, P-DSPs have the special addressing modes that permit single word/instruction format and thereby speed up the execution by making effective use of the instruction pipelining. Further there also special addressing modes such as cyclic addressing and bit reversed addressing that are specifically tailored for DSP applications. The special addressing modes in P-DSPs are as follows :

Short immediate addressing
Short direct addressing
Memory mapped addressing
Indirect addressing
Bit reversed addressing
Circular addressing

Short immediate addressing

In short immediate addressing mode, the operand is specified as a short constant that forms part of a single word instruction. The length of the short constant depends on the programmable DSP and the instruction type. In TMS320C5XDSPs, an 8 bit constant can be specified as one of the operand in the single word instruction like AND, OR, addition, subtraction, etc.

Short direct addressing

In short direct addressing mode, the lower order address of the operand is specified in the single word instruction. In TITMS320DSPs, the higher order 9 bits of the memory are stored in the data page pointer and only the lower 7 bits are specified as part of the instruction, Using short direct addressing in the Motorola DSP600X processor, an instruction is specified with a 6 bit address.

Memory-mapped addressing

In this addressing mode, the CPU registers and the I/O registers are accessed as memory locations by sorting them in either the starting page or the final page of the memory space. For example, in TMS320C5X, page 0 corresponds to the CPU registers and I/O register.

In case of Motorola DSP5600X, the last page of the memory space containing 64 locations is used as the memory map for the CPU and I/O registers.

Indirect addressing

This addressing mode has a number of options in P-DSPs. This mode permits an array of data to be efficiently processed, fetched and stored. The address of the operands can be stored in one of the registers called indirect address registers. In the case of TI processors, the indirect address registers are called auxiliary registers ARs. When the operands fetched by these registers are being executed, these registers can be updated. This is made possible by having an additional ALU in the CPU core specifically for the indirect address registers of ARs.

Bit reversed addressing

The binary pattern corresponding to a particular decimal number is obtained by writing the natural binary equivalent of the number in the reverse order. Therefore, the least significant bit of the bit reversed number becomes the most significant bit of the natural binary number and vice versa. In this addressing mode, the address is incremented or decremented by the number represented in the bit reversed form.

Circular addressing mode

In real time processing of signals, the input signal is continuously stored in memory. The processed data is stored in another memory space continuously and may be written on to the output device. In this case, the input as well as output program will be simple. However, since the input as well as the output memory space is finite it would be exhausted after processing the input signal for some time, if the data is written into the memory by using linear addressing mode. This problem may be overcome by checking continuously whether the range of either the input or the output memory space is exceeded. In that case, the new data is to be stored starting from the beginning of the particular memory space. Checking this condition is an overhead that can be overcome using the circular addressing mode.

Hardware Software Co-Design

Fundamental Issues in Hardware Software Co-Design

1. Selecting the model

2. Selecting the architecture

3. Selecting the language

4. Partitioning system requirements into Hardware and Software

1. Selecting the model

Models are used for capturing and describing the system characteristics
A model is a formal system consisting of objects and composition rules
Designers switch between variety of models from the requirements specifications to the implementation aspect of the system design
Specifications stage --> functionality
Implementation stage --> system components, system structure

2. Selecting the architecture

Architecture specifies how a system is going to implement in terms number of and type of different components and their interconnection

Architecture are controller architecture, Datapath architecture, Complex Instruction Set Computing(CISC), Reduced Instruction Set Computing (RISC), Very long Instruction Word (VLIW), Single Instruction Multiple Data (MIMD)

Application specific architecture class -> Controller architecture, etc.
General purpose architecture class -> CISC, RISC, etc.
Parallel processing class -> VLIW, SIMD, MIMD, etc.

a) Controller architecture

Implements the finite state machine model using a state register and two combinational circuits
State register holds the present state, and
Combinational circuits implement the logic for next state and output

b) Datapath architecture

Implements the data flow graph model
The output is generated as a result of a set of predefined computations on the input data
Datapath represents a channel between the input and output
Datapath contain registers, counters, register files, memories and ports, high speed arithmetic units

c) Finite State Machine Datapath (FSMD)

Combines controller architecture with data-path architecture
It implements a controller with data-path
Controller generates the control input
Datapath processes the data
Datapath contains two types of I/O ports

Control port for receiving/ sending the control signals from / to the controller unit
Datapath port interfaces the external world for data input and data output

Datapath is implemented in a chip

d) CISC

Use of a single complex instruction in place of multiple simple instructions reduces the program memory access and program memory size requirement
Datapath for CISC is complex
EX: CJNE instruction for 8051 ISA

e) RISC

Uses Instruction set representing simple operation
Datapath of RISC architecture contains a large register file for string operands and output
RISC supports pipelining

f) VLIW

Implements multiple functional units(ALU'S, multipliers, etc.) in the data-path
VLIW instruction packages one standard instruction for functional unit of data-path

g) Parallel processing architecture

Implements multiple concurrent processing elements (PEs) and each PE associates a data-path containing register and local memory
SMID --> Single instruction is executed in parallel with the help of PEs
Single controller schedules the instruction execution and controls each PE
SMID forms basis of re-configurable processor
MIMD--> PEs execute different instructions at a given point of time
MIMD forms the basis of multiple processor systems
PES communicates through mechanism like shared memory and memory passing

3. Selecting the language

Language should capture the computational model easily and maps it into architecture
Software implementation --> C, C++, C#, Java, etc.
Hardware implementation --> VHDL, System C, Verilog, etc.
A single language can be used for capturing a variety of models
EX: C++ captures an object oriented model

4. Partitioning System Requirements into Hardware and Software

From implementation point of view, it may be possible to implement the system requirements in either hardware or software (firmware)

VLIW ARCHITECTURE

Very long instruction word (VLIW) architecture is another architecture used for P-DSP's (Example:TMS320C6X).
The VLIW processor consists of architecture that reads a relatively large group of instructions and executes them at the same time.
These P-DSP's have a number of processing units (data paths).
In other words, they have a number of ALU's, MAC units, shifters etc.
The VLIW is accessed from memory and is used to specify the operands and operations to be performed by each of the data paths.
The VLIW processing increases the number of instructions that are processed per cycle. The multiple functional units share a common multi-ported register file for fetching the operands and storing the results.
The read/write cross bar provides parallel random access by multiple functional units to the multi-ported register file.
Execution of the operations in the functional units is carried out concurrently with the load/store operation of data between a RAM and the register file.
The performance gains that can be achieved with VLIW architecture depends on the degree of parallelism in the algorithm selected for a DSP application and the number of functional units.
The through put will be higher only if the algorithm involves execution of independent operations
For example by using eight functional units, the time required for convolution can be reduced by a factor of 8 compared to the case where a single functional unit is used.
However, it may not always be possible to have independent stream of data for processing.
Further the number of functional units is also limited by the hardware cost for the multi-ported register file and cross bar switch.

FPGA Design Flow

DSP IMPORTANT QUESTIONS

UNIT-1

1..Define periodic signal and illustrate problems ?
2 Find the step response of a discrete-time LTI system whose difference equation is given by

y(n)=y(n-1)+0.5y(n-2)+x(n)+x(n-1)

3. Define and explain the following systems with an example: (i) Causual and non-causual (ii) Time-invarient and time-varient
4. Find the magnitude and phase response of the LTI system with

h(n)=x(n)-x(n-1)

5. Determine the causality and stability of the following systems with impulse response (i). h(n)=3ⁿu(-n) (ii). E²ⁿu(n-1)
6. Define and explain the following discrete-time signals with necessary mathematical expressions :(i) periodic and aperiodic (ii) Energy and power
7. State and prove the frequency shifting property of DTFT.
8. Explain the digital signal processing &block diagram and classify their signals?
9. Discuss the frequency domain representation of linear time-in variant systems?
10.Determine the all systems with illustrate problems ?

UNIT-2

11Find the DFT of the following sequence using DIF FFT x(n)={1,2,3,5,5,3,2,1}
12. Find the inverse FFT of x[k]=[10,-2+j2,4,-2-2j]
13.Compute the DFTS of the sequence x(n)=2^-n where N=8 using DIT algorithm ?
14. State and prove any four properties of discrete fourier series (DFS) ?
15. Explain the significance of FFT algorithms. Draw the basic butterfly diagram for radix-2 DIT FFT ?
16. Find the linear convolution of the sequence x(n)={1,4,0,9,5} and h(n)={-3,-4,5,6,8} and related problems
17.State and prove the convolution properties of DFT ?
18. How FFT algorithm improves the speed of computation? Explain with an example ?
19. Find the 4-point DFT of the sequence x(n)={2,1,3,4} by using DIF FFT algorithm ? also, plot its magnitude and phase spectra ?
20. Explain the procedure to compute 8-point DFT using DIT FFT algorithm ?
21. Distinguish between linear convolution and circular convolution ?
22. Develop a radix-2 DIT FFT algorithm for evaluating 4-point DFT . also draw its flow diagram ?

UNIT-3

23. Explain Transposed Forms ?
24.Obtain the direct form I and direct form II and cascade form realization of the following system functions
y(n)=0.1y(n-1)+0.2y(n-2)+3x(n)+3.6x(n-1)+0.6x(n-2) model problems ?

25.Obtain the parallel form realization for the IIR system described by the transfer function

H(z)=3+3.6z^-1+0.6z^-3/1+0.1z^-1-0.2z^-2

26. Realize H(z)=1+0.6z^-2+0.2z^-1/3+5z^-1+4z^-2 using Direct form I and Direct form II structures
27. Compare Chebyshev filter and Butterworth filter
28.Obtain the cascade form realization for the recursive IIR system described by the transfer function H(z)=3+3.6z^-1+0.6z^-2/1+0.1z^-1-0.2z^-2
29.Explain the analog filter to Digital filter?
30. Obtain the 4^th order transfer function of normalized Butterworth low pass filter ?
31.List out the requriements for conversion of stable analog filter into stable digital response ?
32. Find H(z),for a 3^rd order Butterworth filter using impulse invariant transformation method . Assume T=1 sec .

UNIT-4

33. Explain FIR filter design using windowing method
34. Comparision of IIR & FIR filters ?
35. Explain the need for the use of window sequence in the design FIR filter. Describe the window sequence generally used and comparable properties ?
36.Write the characteristics of FIR Digital filters ?
37.Explain about the basic structure of FIR system ?

38.Design of FIR Digital filters using window technique and frequency sampling tech wave?

UNIT-5

39.Explain different pipeline programming models that are adapted in DSP processor ?
40.Explain the cortex-M3 and cortex-M4 processors architecture and draw their block diagram ?
41. Explain memory access schemes in DSPs ?
42. Explain the memory interface block diagram for the TMS320C5X processor ?
43.What are the various addressing modes used in the TMS320C5X processor ?
44. With examples explain the different addressing formats supported by DSP processor for various signal processing applications ?
45.Explain the following i) on-chip peripherals ii)VLIW architecture iii) special addressing modes

IMPORTANT QUESTIONS

VLSI IMPORTANT QUESTIONS

UNIT - 1

1) Derive the relationship between drain and source current Ids versus drain to source voltage Vds in a non-saturation and saturation region?

2) What are the involved in the given fabrication process? Explain with neat sketch i)nmos ii)pmos iii)cmos
3) Compare Bicmos technology with other technologies?
4) Design a stick diagram for i)nmos logic Y=(A+B+C)whole bar ii)for cmos logic Y=(A+B+C)whole bar?
5) Explain with suitable examples how to design the layout of a epte to maximum performance and minimize area?
6) Compare the relative merits of three different forms of pull-up for an inverter circuit? What is the best choice for realization in nmos and cmos technology?
7) Explain the concept of VLSI design flow and flowchart of VLSIdesign flows & write the domain of VLSI design flow and Y chart of design flow?
8) What is a stick diagram? Draw the stick diagram and layout for cmos inverter?
9) Derive an expression for transconductance of an n-channel enhancement MOSFET operating in active region ?
10) Explain about 2micrometer CMOS design rules and discuss with layout examples ?

UNIT -2

11) What is meant by sheet resistance (Rs) ? Explain the concept of Rs applied to the mos Transistors ?
12) What is inverter delay? How delay is calculated for multiple stages ? Explain ?
13)Calculate on resistance of an inverter from Vdd to GND?( Illustrate Problems)
14)Explain the issues involved in driving large capacitor loads in VLSI circuit regions ?
15)Explain the scaling models & factors for device parameters?
16) Explain the limits on logic levels and supply voltage due to noise and current density ?
17) Explain the driving large capacitive loads & propagation delays and of layers ?
18)Design a 2-input Ex-OR using CMOS Transmission gate ?
19) Discuss about choice of fan-in and fan-out selection in gate level design ?

UNIT – 3

20) Explain about regions of operations of MOSFET & modelling of transistor ?
21)Explain how MOSFET acts as a current sources & current sintcs ?
22) Explain the operation of common source MOSFET amplifier with diode connected load & resistive load ?
23) With a neat sketch explain the operation of CS stage with current source load . Also derive its voltage gain ?
24)With a neat sketch describes the operation of common gate amplifier. Also derive its voltage gain ?
25) Describe the operation of source follow (common drain). What are the merits and demerits ?
26) What is current mirror ? Explain the general properties of current mirror with block diagram ?
27) Explain the operation of single stage amplifier with resistive load ?

UNIT – 4

28) Explain the concept of complementary cmos gates have static properties ?
29) Explain Master-Slove Edge-Triggered register & bistability principle?
30) Explain the operation of an SR lacth using NAND gates. Implement it with cmos design ?
31)What are the problems occurred in ultra deep submicron(USDM) technology at analog circuit design ? Hoe they overcome ?
32) Explain the issuses in dynamic design & cascading dynamic gates ?
33)Write short notes on the issues of capacitive coupling in dynamic design?
34) Implement the register of question 8 using cmos logic & explain how 0-0 and 1-1 overlap of clock signal are eliminated ?
35) Explain about dynamic power consumption for cmos gate &dissipation due to direct path currents ?
36) Write a short note on i)Ratioed circuits ii)Dynamic circuits

37) Describe pass transistor briefly with examples ?
38) Explain the following i)Static power dissipation ii) Dynamic power dissipation ?

UNIT – 5

39) Explain the FPGA design flow & FPGA architecture ?
40) Explain the FPGA technologies & introduction FPGA families ?
41) Explain the giga scale dilemma ?
42 )Explain about short channel effects ?
43) Explain (or) Write a short note on a FINFET & TFET ?
44)Explain the high -K/ Metal technology ?
45) What are FPGAs? Explain the principle and operation/
46) List out the important features of Altera Flex 8000FPGA ?