SPECIAL ADDRESSING MODES IN P-DSPs
In addition to the addressing modes such as direct, indirect and immediate supported by the conventional microprocessors, P-DSPs have the special addressing modes that permit single word/instruction format and thereby speed up the execution by making effective use of the instruction pipelining. Further there also special addressing modes such as cyclic addressing and bit reversed addressing that are specifically tailored for DSP applications. The special addressing modes in P-DSPs are as follows :
- Short immediate addressing
- Short direct addressing
- Memory mapped addressing
- Indirect addressing
- Bit reversed addressing
- Circular addressing
Short immediate addressing
In short immediate addressing mode, the operand is specified as a short constant that forms part of a single word instruction. The length of the short constant depends on the programmable DSP and the instruction type. In TMS320C5XDSPs, an 8 bit constant can be specified as one of the operand in the single word instruction like AND, OR, addition, subtraction, etc.
Short direct addressing
In short direct addressing mode, the lower order address of the operand is specified in the single word instruction. In TITMS320DSPs, the higher order 9 bits of the memory are stored in the data page pointer and only the lower 7 bits are specified as part of the instruction, Using short direct addressing in the Motorola DSP600X processor, an instruction is specified with a 6 bit address.
Memory-mapped addressing
In this addressing mode, the CPU registers and the I/O registers are accessed as memory locations by sorting them in either the starting page or the final page of the memory space. For example, in TMS320C5X, page 0 corresponds to the CPU registers and I/O register.
In case of Motorola DSP5600X, the last page of the memory space containing 64 locations is used as the memory map for the CPU and I/O registers.
Indirect addressing
This addressing mode has a number of options in P-DSPs. This mode permits an array of data to be efficiently processed, fetched and stored. The address of the operands can be stored in one of the registers called indirect address registers. In the case of TI processors, the indirect address registers are called auxiliary registers ARs. When the operands fetched by these registers are being executed, these registers can be updated. This is made possible by having an additional ALU in the CPU core specifically for the indirect address registers of ARs.
Bit reversed addressing
The binary pattern corresponding to a particular decimal number is obtained by writing the natural binary equivalent of the number in the reverse order. Therefore, the least significant bit of the bit reversed number becomes the most significant bit of the natural binary number and vice versa. In this addressing mode, the address is incremented or decremented by the number represented in the bit reversed form.
Circular addressing mode
In real time processing of signals, the input signal is continuously stored in memory. The processed data is stored in another memory space continuously and may be written on to the output device. In this case, the input as well as output program will be simple. However, since the input as well as the output memory space is finite it would be exhausted after processing the input signal for some time, if the data is written into the memory by using linear addressing mode. This problem may be overcome by checking continuously whether the range of either the input or the output memory space is exceeded. In that case, the new data is to be stored starting from the beginning of the particular memory space. Checking this condition is an overhead that can be overcome using the circular addressing mode.
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