SPECIAL ADDRESSING MODES IN P-DSPs

                      SPECIAL  ADDRESSING MODES IN P-DSPs

 In addition to the addressing modes such as direct, indirect and immediate supported by the conventional microprocessors, P-DSPs have the special addressing modes that permit single word/instruction format and thereby speed up the execution by making effective use of the instruction pipelining. Further there also special addressing modes such as cyclic addressing and bit reversed addressing that are specifically tailored for DSP applications. The special addressing modes in P-DSPs are as follows :

1.  Short immediate addressing
2.  Short direct addressing
3.  Memory mapped addressing
4.  Indirect addressing
5.  Bit reversed addressing
6.  Circular addressing

Short immediate addressing

In short immediate addressing mode, the operand is specified as a short constant that forms part of a single word instruction. The length of the short constant depends on the programmable DSP  and the instruction type. In TMS320C5XDSPs, an 8 bit constant can be specified as one of the operand in the single word instruction like AND, OR, addition, subtraction, etc.

Short direct addressing

In short direct addressing mode, the lower order address of the operand is specified in the single word instruction. In TITMS320DSPs, the higher order 9 bits of the memory are stored in the data page pointer and only the lower 7 bits are specified as part of the instruction, Using short direct addressing in the Motorola DSP600X processor, an instruction is specified with a 6 bit address.

Memory-mapped addressing

In this addressing mode, the CPU registers and the I/O registers are accessed as memory locations by sorting them in either the starting page or the final page of the memory space. For example, in TMS320C5X, page 0 corresponds to the CPU registers and I/O register.

               In case of Motorola DSP5600X, the last page of the memory space containing 64 locations is used as the memory map for the CPU and I/O registers.

Indirect addressing

This addressing mode has a number of options in P-DSPs. This mode permits an array of data to be efficiently processed, fetched and stored. The address of the operands can be stored in one of the registers called indirect address registers. In the case of TI processors, the indirect address registers are called auxiliary registers ARs. When the operands fetched  by these registers are being executed, these registers can be updated. This is made possible  by having an additional ALU in the CPU core specifically  for the indirect address registers of ARs.

Bit reversed addressing

The binary pattern corresponding to a particular decimal number is obtained by writing the natural  binary equivalent of the number in the reverse order. Therefore, the least significant bit of the bit reversed number becomes the most significant bit of the natural binary number and vice versa. In this addressing mode, the address is incremented or decremented by the number represented in the bit reversed form.

Circular addressing mode

In real time processing of signals, the input signal is continuously stored in memory. The processed data is stored in another memory space continuously and may be written on to the output device. In this case, the input as well as output program will be simple. However, since the input as well as the output memory space is finite it would be exhausted after processing the input signal for some time, if the data is written into the memory by using linear addressing mode. This problem may be overcome by checking continuously whether  the range of either the input or the output memory space is exceeded. In that case, the new data is to be stored starting from the beginning of the particular memory space. Checking this condition is an overhead that can be overcome using the circular addressing mode. 

                          

                   Hardware Software Co-Design

   Fundamental Issues in Hardware Software Co-Design

1. Selecting the model

2. Selecting the architecture

3. Selecting the language

4. Partitioning system requirements into Hardware and Software

1. Selecting the model 

• Models are used for capturing and describing the system characteristics
• A model is a formal system consisting of objects and composition rules
• Designers switch between variety of models from the requirements specifications to the implementation aspect of the system design
• Specifications stage --> functionality
• Implementation stage --> system components, system structure

2.  Selecting the architecture

       Architecture specifies how a system is going to implement in terms number of and type of different components and their interconnection

      

      Architecture are controller architecture, Datapath architecture, Complex Instruction Set Computing(CISC), Reduced Instruction Set Computing (RISC),  Very long Instruction Word (VLIW), Single Instruction Multiple Data (MIMD)

1. Application specific architecture class -> Controller architecture, etc.
2. General purpose architecture class -> CISC, RISC, etc.
3. Parallel processing class -> VLIW, SIMD, MIMD, etc.

a) Controller architecture

• Implements the finite state machine model using a state register and two combinational circuits
• State register holds the present state, and
• Combinational circuits implement the logic for next state and output

b) Datapath architecture

• Implements the data flow graph model
• The output is generated as a result of a set of predefined computations on the input data 
• Datapath represents a channel between the input and output
• Datapath contain registers, counters, register files, memories and ports, high speed arithmetic units  

c) Finite State Machine Datapath (FSMD)

• Combines controller architecture with data-path architecture
• It implements a controller with data-path
• Controller generates the control input
• Datapath processes the data
• Datapath contains two types of I/O ports

1.  Control port for receiving/ sending the control signals from / to the controller unit
2.  Datapath port interfaces the external world for data input and data output

•  Datapath is implemented in a chip

d) CISC

•  Use of a single complex instruction in place of multiple simple instructions reduces the program memory access and program memory size requirement
• Datapath for CISC is complex
• EX: CJNE instruction for 8051 ISA

e) RISC

•  Uses Instruction set representing simple operation
•  Datapath of RISC architecture contains a large register file for string operands and output
•  RISC supports pipelining

f) VLIW

•  Implements multiple functional units(ALU'S, multipliers, etc.) in the data-path
•  VLIW instruction packages one standard instruction for functional unit of data-path

g) Parallel processing architecture

• Implements multiple concurrent processing elements (PEs) and each PE associates a data-path containing register and local memory
•  SMID --> Single instruction is executed in parallel with the help of PEs
• Single controller schedules the instruction  execution and controls each PE
• SMID forms basis of re-configurable processor
• MIMD--> PEs execute different instructions at a given point of time
• MIMD forms the basis of multiple processor systems
• PES communicates through mechanism like shared memory and memory passing

3. Selecting the language

• Language  should capture the computational model easily and maps it into architecture
•  Software implementation --> C, C++, C#, Java, etc.
•  Hardware implementation --> VHDL, System C, Verilog, etc.
• A single language can be used for capturing a variety of models
• EX: C++ captures an object oriented model

4. Partitioning System Requirements into Hardware and Software

• From implementation point of view,  it may be possible to implement the system requirements in either hardware or software (firmware)